资源列表
uart_tx_rx
- 在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。-Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debuggi
PWM_music
- 在altera的FPGA平台上，使用verilog语言实现蜂鸣器的音乐，内含乐谱理论和verilog实现的FPGA奏乐代码与工程，已经测试通过，可以直接下载到FPGA运行，蜂鸣器播放音乐。-In the Altera FPGA platform, using Verilog language to achieve the buzzer music, FPGA music code and engineering including music theory and implementation
A8237
- Altera Quartus Megacore of A8237 (DMA Controller). Published by Altera for free after the IP Megacore portfolio has changed.
A8251
- Altera Quartus Megacore of A8251 (UART). Published by Altera for free after the IP Megacore portfolio has changed.
A8255
- Altera Quartus Megacore of A8255 (3x8Bit PIO). Published by Altera for free after the IP Megacore portfolio has changed.
A8259
- Altera Quartus Megacore of A8259 (IRQ Controller). Published by Altera for free after the IP Megacore portfolio has changed.
IIC
- verilog编写，京微雅格出品IIC 控制器-IIC controller，writed by YiJingjing
all-pole_filters_latest.tar
- All polar vector and its vhdl code with testbench
nios2PtfcardPvga
- 使用nios的io管脚模拟spi时序对tf卡进行数据读写，同时附带一个简单的用verilog写的在vga显示器上刷屏的代码-Use the io pin of nios to simulate the timing of spi to read&write date from&to tf card, and comes with a simple code written by verilog to refresh the vga monitor.
source
- IO转UART的数据收发控制和收发数据代码，中文注视，能够清楚了解代码含义-IO UART data transceiver control and send and receive data code, Chinese gaze, knowing code meaning
adc_test
- verilog AD采样源代码，包括test代码-verilog AD
Sawtooth_Wave
- verilog写的锯齿波程序，基于DDS原路的。内含testbench仿真文件。功能十分强大-verilog write sawtooth program, based on the same route of DDS. Embedded testbench simulation files. Is very powerful