资源列表
multi
- 实现带时钟的四比特正数相加，一个顶层文件和一个tb文件-4 bit multiply
EDA-clock
- 基于FPGA的时钟设计,主要能实现计时和日历功能-The clock design based on FPGA, the main can realize clock and calendar function
Sum
- 实现加法器功能的简单verilog代码，可以为初学者提供学习。-Achieve a simple verilog adder function code can provide learning for the beginners.
BASYS2
- xilinx公司basy2开发板入门教程.-xilinx development board company basy2 Tutorial.
Frame_Detection
- OFDM系统的帧检测模块，根据802.11a标准，利用前导的相关性进行的设计，综合仿真及在线调试已通过。-Ofdm frame detection module is very important and verilog difficult to realize in OFDM system.
PSG
- Altera NIOS II 使用的 AY-3-8910 模組 . 包含 AY-3-8910 Verilog code, SOPC builder使用的hw_tcl及R-2R DAC 電路-AY-3-8910 module for Altera Nios II. verilog source code, hw_tcl file and R-2R DAC schematic.
spectrum_system_back
- 完成对干涉数据光谱反演的一系列操作：FFT及相位对齐参数的计算。-Completion of the interference spectrum inversion of the data series of operations: FFT and phase alignment parameter calculations.
VHDL Digital Clock
- A digital stop watch designed in VHDL
verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台，结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
38coder
- 实现一个38译码器电路功能的vhdl代码。-Realizing the function of a decoder circuit 38 VHDL code.
Vrilog-hdl--Sequence-check.doc
- 用VrilogHDL编写的一个序列检测器-use rilogHDL define a Sequence check Instrument
rs_decoder_31_19_6_latest.tar
- 31.19解码器- RS code is the BCH code of multi-systerm, after a long time of development, the theory and technology of RS code has been rather mature that it can rectify burst error and random error at the same time, especially burst error. It is widel