资源列表
DS18B20_ysd
- 18b20 verilog fpga ep3c10e
Periphery_For_FPGA
- fpga开发资料，英文版datasheet-fpga development information, English datasheet
usb2.0-verilog-hdl
- usb2.0协议层的verilog hdl实现-usb2.0 protocol layer implementation verilog hdl
is95receiver
- CDMA IS-95 接收机基带处理仿真 对扩频原理学习有所帮助-CDMA IS-95 receiver
source
- SDRAM 控制, 用於SDRAM上 的代碼-SDRAM Control
zonghejishiqi
- 综合性的计时系统，要求能实现年、月、日、时、分、秒及星期的计数等综合计时功能，同时将计时结果通过15个七段数码管显示，并且可通过两个设置键，对计时系统的有关参数进行调整。-Integrated timing system requirements to achieve the year, month, day, hour, minutes, seconds and weeks of counting time features such as integrated, while timing t
TIMER
- 精度为1/10秒的秒表，上电后数码管开始计时，带复位和暂停功能-Accuracy of 1/10 second stopwatch, starting on time after power LED, reset and pause with
VHDL
- vhdl分频代码，只需改变里面的常数即可，改变分频系数-vhdl frequency code, just a constant which can be changed to change the frequency factor
VHDL
- vhdl交通灯程序，包括波形测试文件和交通灯控制文件。-vhdl traffic light procedures, including wave test file and traffic light control file.
lab2
- 使用chdl 实现音谱转换的小实验，可以作为音乐翻译的样子-Convert audio spectrum using chdl achieve a small experiment, translated as the way music
uart-con
- This is a vhdl file for implementing UART.
PWM-DCMotor-Control-based-on-VHDL
- 基于VHDL的直流电机的PWM控制程序，用vhdl语言写的直流电机控制程序-PWM DC Motor Control Program based on the VHDL