资源列表
rsencoder
- DVB-C/T调制器的reed-soloman encoder代码-DVB-C/T modulator of reed-soloman encoder code
crk_rscodec
- altera 的reed-soloman codec代码-The reed-soloman codec altera code
FIR-design
- FIR滤波器设计的一些论文资料，对于设计FIR滤波器比较有帮助-Some of the papers FIR filter design information, design of FIR filters for more helpful
multi_bank_OLD
- A expensive MultiBank Algorithm for DVB Deinterleaving
VHDL
- 本人上传的是关于嵌入式单片机开发语言VHDL的学习教程资料。希望对大家的学习有帮助。-I uploaded is about the development of embedded microcontroller VHDL language learning tutorial information. Hope to learn helpful.
chengxu
- 基于FPGA的DDS信号发生器设计，可以运行并出结果-The spurious signal generator based on FPGA design，Can run and out the results
1-5
- 5个Spartan-3e开发板的国外大学的使用源码。学习好资料。-5 Spartan-3e development board to use source of foreign universities. Study and information.
vga
- vga显示，可以用fpgavga连接显示器显示彩条，简单实用的verilog程序-vga display, you can connect with fpgavga display color bars, simple and practical procedure verilog
crc
- For implementing the CRC in verilog or VHDL
ecc
- For implementing the Hamming coding in verilog or VHDL
DRAMsimManual
- DRAM simulator implemented in verilog/VHDL
lock-and-lcd
- 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码