资源列表
redwire
- 基于FPGAEASY060的红外发送，接收及数码管显示-Based on the FPGAEASY060 infrared sending, receiving and digital tube display
Find_The_Prime
- VHDL 代码，用于查找一个数列的素数搜寻器。-Prime Number comparator
VGA_PS2
- 使用键盘控制显示器上矩形框的移动。使用verilog HDL编写。已经在spartan3-E开发板上实现。保证好用。-Use the keyboard to control the movement of the display rectangle. Prepared using verilog HDL. Has been achieved spartan3-E on the development board. To ensure ease of use.
Verilog
- verilog使用入门教程。十分适合初学者阅读。word文档中有很多编程经验，很值得借鉴。很好的东西。-verilog Getting Started tutorial. Very suitable for beginners to read. word document, there are many programming experience, it is worth learning from. A good thing.
CRC
- 基于VHDL的CRC编解码器设计，非常好用的哈。我的毕业设计内容-The CRC VHDL-based codec design, very easy to use, ha. The contents of my graduation
FPGA_UWB
- 基于FPGA的UWB的发射系统.caj -UWB FPGA-based launch systems. Caj UWB FPGA-based launch systems. Caj
sclock_01
- verilog 秒表，利用视觉暂留，时钟频率-verilog stopwatch
0471441481
- design through verilog HDL
CummingsSNUG2000SJ_NBA_rev1_2
- Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
the_complete_verilog_book
- the complete verilog book
WCE2009_pp376-381
- A Simple Digital VHDL QPSK Modulator Designed Using CPLD/FPGAs for Biomedical Devices Applications
clk
- 时钟的产生和测试 ，并采用了状态机的方法-Clock generation and testing, and using the state machine approach