资源列表
modelsim6.0
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。-Mentor' s ModelSim is the industry' s best HDL language simulation software, it can provide a friendly simulation environment, the industry' s only single-kernel
ise11tut
- Verilog语言开发环境ISE例程，适合于初学者-ISE Verilog language development environment routines, suitable for beginners
wtut_ver
- Verilog语言开发环境ISE例程，适合于初学者-ISE Verilog language development environment routines, suitable for beginners
wtut_vhd
- Verilog语言开发环境ISE的一些例程，适合于初学者-ISE Verilog language development environment for a number of routines, suitable for beginners
sp601_BIST_rdf0045_12.4_c
- Xilinx开发板sp601的开发实例，适用于初学者-Xilinx development board sp601 development example for beginners
testbench
- 介绍如何编写verilog的仿真程序，很适合初学者-How to write verilog simulation program, it is suitable for beginners
VerilogHDL
- 很多verilog编写实例，简单易行，很适合初学者-Verilog written many instances, simple, very suitable for beginners
my_kmp_matching
- KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
paomadeng
- FPGA led实现8个跑马灯四个模式的装换-FPGA led Marquee
vhdl-fifo
- vhdl 语言实现fifo功能模块 包含接口：clk、data_in、data_out-fifo use vhdl
VHDL-CODES
- here are some vhdl codes for decoder ,mux electronis circuits
play-a-song
- 通过VHDL编程，控制下位机播放歌曲梁祝。-Through the VHDL program, under the control of the crew playing the song Butterfly.