资源列表
fir_comm
- 用QUARTUS软件，实现一个32阶的FIR数字滤波器-QUARTUS software used to implement a 32-order FIR digital filter
xianbo
- 以DE2为平台，用QUARTUS软件实现一个数字陷波器-To DE2 as a platform, software with a digital QUARTUS notch filter
fir_da_test
- 用QUARTUS软件，用DA算法实现一个32阶的FIR滤波器-QUARTUS software used with the DA algorithm to achieve a 32-order FIR filter
iir_16
- 用QUARTUS软件实现一个16阶的IIR滤波器-QUARTUS software with a 16-order IIR filter
Digital_Phase_Measurement
- 测量相位差并用LCD显示。从信号源接入两路信号,经过AD1和AD2转换后，送入FPGA中。 在FPGA中，使用双值法整形，得到两路标准的方波，然后测出两路信号的时差Δt，以及信号的周期T， 并计算相位差（ΔΦ=Δt/T*360°）。并送入1602中显示。经测试，其测相误差小于1 。-Measured phase difference and with LCD display. Two-way access from the source signal, converted by AD1
Generic_NOR3_gate_design
- 设计一个带类属参数的或门，它有N 个输入，N 的默认值为3。在顶层元件中将该类属元件例化2 次。在一个元件中将类属参数改变为N=4，而在另在一个元件中改变为N=5。-The way of using generic in VHDL design is shown in the Ninput NOR gate.
[f
- 只能小车C8051，智能小车C8051的程序设置，有用的来看看
LEON3
- 基于LEON3核的在线调试工具开发 基于LEON3核的在线调试工具开发-On-line debugging tools LEON3 nuclear development based on-line debugging tools LEON3 development of nuclear
LEON3.Speed.SoC
- 基于LEON3处理器和Speed协处理器的复杂SoC设计实现-Speed based on LEON3 processor and the complexity of co-processor SoC design and implementation
CUDA-CPU-GPU
- 跟大家深入到CUDA的内部，为大家诠释为什么说：唯有NVIDIA CUDA才是终极的CPU-CUDA with you deep into the interior, as we interpret why: Only the CPU is the ultimate NVIDIA CUDA
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
LinPF
- This a VHDL module that implements linear prediction filter based on NLMS (normalized least mean square). The module takes complex signal as input and output comlex signal (real and imaginary). Tap size is 4, bit precision is set to 12 bits.-This i