资源列表
123
- 这是数字信号处理的FPGA实现的光盘里面的源代码，里面VHDL 和verilog 两种语言都有-This is a digital signal processing inside the FPGA implementation of the source code of the disc, there are two languages VHDL and verilog
manic.tar
- mp3 player embeded system
samlecode.vhdl
- This document lists the basic function of a vhdl code including the entity and ending with archetecture. Also it has a sample code of pwm vs sigma delta signals output.
samlecode.vhdl
- THis code describes how to use the pwm singal generator and how to generate this using VHDL>
VHDL
- 基于hdl的交换机设计，学习的人可以看一下-Hdl-based switch design, the study of people can look at
Verilog-HDL-xiayuwen
- 夏宇闻老师的经典教程，对Verlag语言感兴趣的朋友或初学FPGA的朋友是个不错的教程。-XIA Wen classic tutorial teachers, the language of the Verlag FPGA beginner interested friends or friends is a good tutorial.
TERASIC_ISP1362
- sopc中ISP1362的IP核，经验证，可以使用，保证正确！-sopc the ISP1362 the IP core, proven, you can use to ensure correct!
5
- 接口代码，利用元件理化思想，将系统分模块设计，并具有各个模块代码-Interface code, the use of physical and chemical components thought the system sub-module design, and code with each module
spartan3IBIS
- Spartan III FPGA IBIS Model
gj-2s
- 基于赛灵思EXCD-1的FPGA开发板，使用ISE10.1开发环境，使用VHDL语言编写，功能为计算输入方波的频率。输入方波，输出方波的频率，用数码管显示，每2s更新一次。管脚配置见工程。-Based on the FPGA Xilinx EXCD-1 development board, using ISE10.1 development environment, using the VHDL language, functions for calculating the frequency
verilogadc0809
- verilog adc0809控制器FPGA实现，编译通过，系统时钟分频，满足ADC时钟要求。-verilog adc0809 controller FPGA, compiler, system clock frequency to meet the requirements of ADC clock.
vhdl
- VHDL与数字电路设计实验代码，可以轻松学会VHDL-VHDL and Digital Circuit Design Experiment code, you can easily learn to VHDL