资源列表
VGA
- 用verilog在quartus环境下开发VGA彩色信号显示-verilog，quartus，vga
keyboard
- sparten 3E 开发板中按键盘，led灯变化的程序，verilog语言-sparten 3E development board in the keyboard, led lights change procedures, verilog language
wo
- sparten 3e开发板的旋转旋钮控制led灯的程序，verilog实现-sparten 3e development board led lamp rotary knob control procedures, verilog implementation
MYPROJECT
- 芯片与FPGA的接口代码,实现以太网10兆的接口方案之源代码-CP2200 & FPGA
Storm
- Storm可以同时对蛋白序列进行BLASTFASTAPfamProtParam分析软件并将结果输出到数据库中.zip-Storm can be BLASTFASTAPfamProtParam of protein sequence analysis software and the results output to the database. Zip
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
cf_interleaver_6_16
- 6*16交织器的实现，非常有用，希望对你有所帮助-6*16interleaver
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xx
Teletext_Core_Files_890607
- A teletext extraction source code for WST PAL B standard
mem64_to_pcitarget_verilog
- This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory -This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunctio
pcitarget_disconnect_verilog
- This design shows how to implement a disconnect of a pci target instantiation of Altera s pci megafunction