资源列表
S3_WAVE
- 用Altera公司生产的FPGA仿真SignalTAP程序，用QuarusII6.0编译 -Produced using Altera FPGA simulation SignalTAP program, compiled with QuarusII6.0
Synopsys_Graphical_Environment_User_Guide
- Synopsis软件图形界面操作指南，对FPGA/ASIC初学者很有用！-Synopsis software GUI operation guide for the FPGA/ASIC is useful for beginners!
digitaldesignwithPLD
- 可编程的逻辑电路，利用VHDL语言实现的时序和组合电路-Programmable Logic
fallthrough_small_fifo_v2
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short
verilog
- 不同Verilog 语言间的差异，以及高版本Verilog语言的特性-Differences between different Verilog language and Verilog language version of the characteristics of high
modelsim6.0
- modelsim 中文使用手册，希望对想学习mldelsim的人有用-modelsim Chinese user manual, and they hope people who want to learn a useful mldelsim
matrix
- 3x3 matrix implementation in VHDL
cFFT
- CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be differen
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
lowpowerfir
- This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst
crc
- 用verilog实现串进并出的CRC算法-Achieved with verilog into and out of the CRC series algorithm
spacewar_final
- 一款用VHDL编写的飞机大战游戏很好很实用-a game by VHDL