资源列表
pci_mini_latest.tar
- pci的代码，有利于关于PCI核的使用，帮助更多的人去学习-pci
pn
- 基于Xilinx的ISE9.0编译的周期为63的m序列-Compiled based on Xilinx' s ISE9.0 63 m sequence of period
DE2LCD_(VHDL)
- DE2控制LCD显示(VHDL编写对LCD的控制)-DE2 LCD
bb
- 2选1的数据选择器 实现2选1的电路功能，其真值表和电路符号如下图所示。即当s＝1时，输出m＝y；当s＝0时，输出m＝x。 -2 Select a data selector circuit to achieve 2 S 1 function, its truth table and circuit symbols shown below. That is, when s = 1, the output m = y when s = 0, the output m = x.
cc
- 在完成2选1数据选择器之后，将信号x和y的位宽由1位扩展为8位-Upon completion of the data selector 2 S 1 after the signal x and y of the bit width from 1 to 8-bit extensions
dd
- 在完成2选1电路之后，将电路扩展为4选1数据选择器-2 S 1 in the complete circuit, the circuit will be extended to 4 S 1 data selector
ee
- 一个七段解码器模块，c2～c0是解码器的3个输入，当输入值不同时，输出不同的字符。如表中所示，当输入值为100～111时，输出空格，即数码管全暗。七段数码管的不同段位用数字0～6表示，注意七段数码管是共阳极的，即各管段输入低电平时，数码管亮；否则数码管暗。 -A seven-segment decoder module, c2 ~ c0 is a 3 input decoder, when the input value is not the same time, the output of d
chap7
- Mux2 1 2 1的乘法器 利用Verilog语言进行编写 -Mux2 1 2 1 multiplier written using Verilog languages
seg
- 用verilog语言实现数码管控制工作，有问题可以qq咨询，516998649-use the verilog language to drive the seg
SPIVerilogHDL
- SPI协议Verilog HDL程序包用Verilog语言实现fpga模拟实现spi协议功能-fpga-spi-verilog
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
Verilog1C21B21A4_1237797332
- Verilog HDL Introduction 1.1 Verilog HDL Introduction 1.2 The basic concept of using the Verilog 1.3 Verilog HDL design concept of modular and hierarchical 1.4 Gate-level design module 1.5 data processing module design 1.6 Behavior Model