资源列表
VHDL
- 1.7段数码译码器 2.4人表决器 3.8421码十进制计数器 4.9秒减计数器-1.7 Section 2.4 digital decoder person voting 3.8421 yards in 4.9 seconds by a decimal counter counter
fcount
- 频率计的设计实例，在FPGA平台上面验证通过，能测0—99M的任意信号的频率，很实用，希望对大家有所帮助。-Frequency Meter instance, in the FPGA platform, validated by the above, can measure 0-99M of any signal frequency, it is useful, we want to help.
EasyFPGA03
- Easy FPGA030原理图，对设计FPGA最小系统有很大的帮助。-Easy FPGA030 schematics, FPGA minimum system design is very helpful.
meter_bucket_renew
- 实现一个简单的令牌桶算法（按照固定速率向桶中放钱。 传送信息包要按照大小花钱买。 钱够了就送出 钱不够就要等候储蓄 ）-Implement a simple token bucket algorithm (Putting the money into the bucket at a fixed rate and pay the price according to the information size which you need to send. The informati
clock
- 简易始终的verilog源程序，拥有复位和暂停的功能-Simple is always the verilog source code, with reset and pause functions
VGA-LCD
- VGA LCD显示有源代码工程项目文件。-VGA LCD display file source code project.
LCD1602_B
- Verlog- 的LCD1602显示器，显示工程源码程序。-Verlog-the LCD1602 display, display engineering source program.
LCD12864
- LCD12864汉字显示，用VHDL工程的12864显示屏汉字显示-LCD12864 character display, works with VHDL 12864 Chinese character display screen
0101
- Quartus II 除法器，用VHDL语言编写的.除法器。-Divider using VHDL language. Divider
Figure_Models
- 用VHDL设计的基本数字逻辑电路，能实现交通灯、模数转换、数模转换等功能-VHDL design using the basic digital logic circuits, to achieve traffic light, ADC, DAC and other functions
VGA
- Verilog代码可移植到FPGA上，利用VGA显示图像，适合初学者使用。-Verilog code can be ported to FPGA, using VGA display images, suitable for beginners.
EDA_FPGA_363
- FPGA 视频采集代码 寄存器， 视频采集卡 主程序-FPGA verilog