资源列表
additionneurcomplet
- additionneur complet
FPGA_EP2C5
- FPGA最小系统，为学习FPGA好资料哦-miniFPGA,learn fpga chark info
wave_gen
- wave generator in vhdl
ZHILIUDIANJI
- EDA直流电机项目设计，能实现加速 减速 方向控制。-EDA DC project design, to achieve directional control of accelerating and decelerating.
verilog_Carnegie_Mellon_University
- 卡内基梅隆大学verilog讲义-verilog courseware of Carnegie Mellon University
8086IP
- 8086IP Core 源码 VHDL版-8086 IP CORE source code（VHDL）
MIPS_IP
- 经典的RISC 计算死体系MIPS 源码VHDL版-Classic RISC MIPS source computing system for VHDL version of death
eslab1
- eslab cua tran trung uit
Interleaver
- 自己做的交织器，里面包含了交织器的源程序，和交织器的仿真电路文件等等。。。调试后，实现结果正确-Do their own interleaver, which contains the source code interleaver and interleaver circuit simulation files and so on. . . After commissioning, to achieve the right results
RAM
- 上述文件是一个ram的开发过程。。。次过程的程序都是我自己写的。验证结果正确-The file is a ram in the development process. . . Second process procedures are written in my own. Verification result is correct. . .
4bit_switch
- 4 bit switch on altera de2
8bit_switch
- 8bit switch on FPGA with vhdl