资源列表
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
kechengsheji
- 基于VHDL语言的一款功能很好的整点报时计时系统。-VHDL language features based on a very good time the whole point timekeeping system.
ZCYL
- 组成原理课设，设计一个计算N的平方和的微型机，N小于等于8-Composition principle lesson set, design a calculation of the square of N and the microcomputer, N less than or equal 8
SystemVerilog_For_Design_Springer_2nd_Ed_2006
- SystemVerilog For Design (Springer-2nd_Ed-2006)-SystemVerilog For Design (Springer-2nd_Ed-2006)
VerilogDataOfChinese
- Verilog语言练习与讲解中文资料,值得学习和收藏。-VerilogDataOfChinese
15AlteraIP
- 15个Altera的IP核，123456789101112131415-15AlteraIP
myAlteraLib
- myAltera的PCBLib库，包括Cyclone系列,Stratix系列，-myAlteraLib
MASHENGvirlogTutorial
- 麻省理工大学的virlog教程，强烈推荐！-MASHENGvirlogTutorial
decorder
- FPGA驱动LED静态显示,VHDL实现的源码-FPGA-driven LED static display, VHDL source code to achieve
hh
- ad1674的控制程序VHDL 利于初学者掌握AD新片的控制，实现了初始化，采集存储-AD1674 CONTROL VHDL
fpga
- fpga数字电子系统设计与开发 ISE I2C UART usb vga -ISE I2C UART usb vga
VHDL_for_clock
- 基于VHDL语言的数字钟设计，附有完整的程序代码，并有仿真结果。-VHDL-based digital clock design, with a complete code, and have the simulation results.