资源列表
edacounter
- 用VHDL语言编写的计数器，在板子上运行成功，可以循环计数，加减计数，先置数后计数等-Counter with the VHDL language, in the board to run successfully, you can cycle counting, addition and subtraction counting, numbers, counting the first home
mul
- 一个小的乘法器源码和test，初学者可以看看！-Multiplier source and a small test, beginners can see!
altera_avalon_i2c_V90
- I2C IP for Quartus V9.0, can used in SOPC builder.
altera_avalon_i2c_V91
- I2C IP for Quartus V9.0 sp1, can used in SOPC builder.-I2C IP for Quartus V9.0, can used in SOPC builder.
oc_i2c_master_top_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
oc_i2c_master_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
oc_i2c_master_byte_ctrl_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
oc_i2c_master_bit_ctrl_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
PetervrlK_verilog
- Verilog Introduction , a general summary of syntax and structure of Verilog language !
ps2_DE1_HEX
- Display Scancode of PS2 on DE1 board !
buzzer
- 用Verilog HDL写得能给蜂鸣器输出‘哆、唻、米、发、嗦、啦、稀、哆（高音）’声调的程序-Buzzer to give written using Verilog HDL output ' duo, Lai ... ...' tone of the program