资源列表
Divider-design-in-three-ways
- 三种方式设计的分频器（常用于产生秒脉冲）-Divider design in three ways (often used to produce second pulse)
ocidec1
- 基于fpga的硬盘控制器，用vhdl语言编写-The hard disk controller
FPGA_Development_of_full-Gong_Lue
- FPGA开发全攻略— 工程师创新设计宝典-FPGA_Development_of_full-Gong_Lue
havy7128-1
- 一直简单的VHDL学习程序，已经调试通过，望大家下载学习。-VHDL has a simple learning process has been debugging through, hope you download the study.
lcdPROG
- 使用FPGA生成液晶显示的一个时序,并且在液晶上显示完整的图形
NIOS_SOUND
- 用NIOS II做的声音演示程序,可直接下载做为演示,-用NIOS II做的声音演示程序,可直接下载做为演示!!
chap6
- 10个VHDL的经典实例，加法计数器中的进程，任务举例，测试程序，函数-10 VHDL classic example of the counter in the process of addition, tasks for example, test procedures, functions. . .
chap7
- 几十个经典程序，结构描述的4 位级连全加器，1 位全加器，用条件运算符描述的4 选1 MUX-Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc.
graphicallcd_latest.tar
- grapic automatically delete the directory of debug and directory of debug
time
- 电子钟实现 包含数字跑表 万年历 设置三个闹钟 时间，日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
FINAL_OUT.VHD
- this is a vhdl program to test your LCD
v
- verilog code for a synthesizer based on Terasic s Multimedia development board. (MTDB) and Altera FPGA.