资源列表
lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
shukongdianyabiao
- 使用51单片机以及键盘液晶作为人机互动，输入你想输入的电压值，端口就输出相应的二进制数-51 MCU and LCD using the keyboard as a human-computer interaction, input you want to input voltage value, the port on the output of the corresponding binary number
spmem.tar
- Sinlge port RAM VHDL/Verilog design
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
FIFO.tar
- FIFO design VHDL/Verilog design
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
2cout10
- 二位十进制计数器，详细的代码和仿真，并且有VHDL代码和原理图设计-2 decimal counter, the detailed code and simulation, and has VHDL code and schematic design of
opencore_crt
- 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
sopcfpga
- 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
s3ask_ddr2
- DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
FPGADDSVHDL
- 基于FPGA的DDS源码，可用，简单易懂-FPGA-based DDS source code, available, easy to understand
Modelsimstudying
- 看一下教程对学习modelsim的使用很有帮助-Look at the tutorial very helpful in learning the use of modelsim