资源列表
digital_clock
- 本实验设计一个能够显示时、分、秒的数字时钟，时间在七段数码管上显示，显示数字为十进制数。通过开发板上的按键调整数字时钟的时间，分别用四个按键来控制分、时的增减，对于分、时的调整只影响本位，不产生进位或借位。各按键及数码管的功能要求如表1 所示。需要特别说明，因为开发板数码管的显示位宽不够，因此，通过一个开关进行切换选择（如：开,显示时分；关,显示分秒）。-When this experiment to design a display hours, minutes, seconds, digit
UART
- 设计一个具有固定波特率的UART串口收发器，可以实现9600波特率的串口通信，能够与PC机串口进行通信，支持8比特数据位、1比特停止位、无校验、无硬件流控模式。-Designed with a fixed baud rate of UART serial port transceiver can achieve 9600 baud serial communication, able to communicate with the PC serial port, support for 8-bi
FOCT
- 光纤电流互感器的温度测量与温度补偿，里面有uart，IIC，荧光温度计与ds12b20 之间的通讯协议-Temperature measurement and temperature compensation of optical fiber current transformer.There are UART, IIC, between the fluorescence thermometer and ds12b20 communication protocol
iis_m_2
- iis主模块，实现并行数据转成串行数据和音频数据传输的功能。-iis main module, parallel data to serial data transfer and audio data transmission capabilities.
UART_LED
- 单字节uart收发程序，带led指示,verilog quartusII 12.0 -verilog quartusII 12.0 uart-led
CIC-interpolation-filter
- 多级插值CIC滤波器，3级、过采样率为2的8位CIC插值滤波器，系统工作时钟的频率是数据速率的2倍 -Multi-stage interpolation CIC filter 3, an oversampling ratio of eight CIC interpolating filter, the operation clock frequency of the system 2 is twice the data rate
SignaltapII_use
- 简单的使用QuartusII软件中的逻辑分析仪，特别适合初学者学习-Simple to use QuartusII software logic analyzer, especially for beginners to learn
modulsim_use_ise_derectly
- 一个简单的使用modlsim直接调用ise的实例，自己当时写的，通过编写do文件直接用modlsim来调用ise的核文件仿真。仅供学习参考-use modulsim call the ise file derectly by writing do file in the modulsim
multiprocessor_tutorial_final_v1
- 多核处理器系统整个源代码，可以在DE2开发板上运行，请大侠多多指点，-Multi-core processor systems throughout the source code can be run in the DE2 board, heroes lot of guidance, thank you
LCD
- 基于vhdl简单的液晶显示电路设计(VHDL desingn)-Display circuit design (VHDL desingn) based on a simple LCD vhdl
counter
- module counter for VHDL on FPGA Kit
tp-vhdl
- A LOT OF LABS ON VHDL MADE AT SCHOOL BY my self A LOT OF LABS ON VHDL MADE AT SCHOOL BY my self