资源列表
EQctrl_20b_edge
- verilog edge type DFE
i2cSlave
- i2c communication slave module
serialInterface
- verilog i2c serial interface module
uart_fifo
- FPGA模拟UART,实现对自发自收. -simulating interface of uart on the fpga
DC_motor
- 为一个直流电机驱动控制程序，包括两个子模块和一个顶层模块，均为verilog源码。-A dc motor drive control code, including two modules and a top-level module, they are all the verilog code.
verilogiic1121
- 用verilog状态机写的IIC通信模块，包括两个子模块和一个顶层模块，均为verilog源码-Written in verilog state machine IIC communication module, including two modules and a top-level module, they are all the verilog code.
VGA
- FPGA通过VGA接口控制显示器显示彩条程序。按键输入，可以改变横条、竖条或方格。-FPGA via VGA interface control display color bar program. Key input, you can change the bar, bars or squares.
PS2
- 原创！FPGA通过PS2键盘输入，在数码管显示输入。-Original! FPGA via PS2 keyboard input, the digital display inputs.
4_BUZZER_PWM
- FPGA通过PWM波控制蜂鸣器产出不同的音调。-FPGA wave PWM control buzzer output by different tones.
src
- FPGA数数码管控制程序，外部接口简单，给出各段数码管的字符即可。-Number FPGA digital control program, the external interface is simple, the characters are given to each segment digital tube.
ML_CTL
- CPLD、FPGA控制8×8点阵显示流水效果-FPGA control dot matrix display water effects.
vhdl
- 8bit latch and a led code