资源列表
clock_retrive_lsy
- 用于E1接口数据时钟恢复，可提取相应的频率-Using for E1 interface, support 2M frequency recovery and retime
CPLD_EXample
- 非常适合新手学习CPLD的例程，从点亮流水灯，到VGA一步一步进阶。-CPLD is very suitable for novices to learn the routines, the lit water lights, step by step advanced to VGA.
project_wave_gen_code
- 设计并实现一个可产生正弦波、三角波和锯齿波的波形发生器。其工作频率为60MHz，可产生1MHz、2MHz、3MHz、4MHz、5MHz、6MHz、10MHz的正弦波、三角波和锯齿波。所产生波形的幅度、相位均可调整，输出数据的字长为12比特。应用环境为quartus 2-Design and implement a can produce sine, triangle, and sawtooth waveform generator. The operating frequency of 60MH
lcd
- 本代码利用verilog语言写的驱动LCD1602 其中LCD1602显示为英文。（LCD带字库）-This code is written in verilog use drive LCD1602 Which LCD1602 display in English. (LCD with font)
ad6655_150
- 该程序是通过FPGA来控制AD6655，通过状态机来改变AD6655寄存器的值，来达到控制目的，实测可用-The program is controlled by FPGA AD6655, AD6655 register value is changed by the state machine, for control purposes, Found Available
regfor24
- 这是一个24小时时钟，整体使用verilogHDL编写，六位数码管显示，分为三个模块，分别为扫频模块，计时显示模块，和顶层模块-it s a clock for 24 hours .use verilogHDL to write the project ,it s easy to understand.
e_piano
- 自己编写的电子钢琴的源码，大家可以下载并且试试，很好用的-I have written an electronic piano source, you can download and try, good use
FIX_ONE_ROW_ROM
- 此為文字型LCD顯示液晶透過矩陣與狀態機顯示內容-This is a text-based LCD display through matrix liquid crystal display with a state machine
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
Lab4
- 此為VHDL之同步清除電路與非同步清除電路之模擬與電路設計-This is a synchronous clear circuit VHDL synchronize with non-clear analog circuits and circuit design of
Lab5
- 此為VHDL之非同步觸發、清除之單擊電路與同步觸發、清除之單擊電路設計-This is a non-synchronous triggering of VHDL, click to clear the circuit and synchronization trigger, click to clear the circuit design
music_ic
- 此為VHDL之音樂IC設計，透過Max Plus II將設計結果顯示。-This is the music of IC design VHDL, designed by Max Plus II results will be displayed.