资源列表
PCM
- PCM码流时隙信号产生模块的VHDL实现-PCM stream slot signal generation module based on VHDL
decoder
- 七段译码器的VHDL实现-The seven segment decoder implementations of VHDL
check
- 11100 码流检测模块的VHDL实现- 11100 stream detection module based on VHDL
counter
- 异步复位的十进制计数器-Decade counter with asynchronous reset
test2
- 此程序为汉字“正”的源程序，仅仅用于学习和交流使用，不当之处，望指正！-This program is the Chinese character " positive" the source, use only for learning and communication, inappropriate, hope correction!
main
- demux impelementation for vhdl muxing protocol
1
- 信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
DE2_Default-source
- Altera FPGA DE2 Default Project File
core
- 串转并的电路转换器，并包含testbench。-The converter circuit about serial to parrel, including testbench.
DOT_LED
- 点亮LED，适用于FPGA 初学者，很不错的例子，简单、易懂-dot led
FPGA-VGA
- 基于FPGA VGA基本显示源码 晶振50M 分辨率 640 x 480-Based FPGA VGA basic source crystal display 640 x 480 resolution, 50M
SRTP2
- 基于FPGA利用verilog HDL编写的128bitAES加密算法电路-Verilog HDL-based FPGA use encryption algorithms written 128bitAES circuit