资源列表
Ch3
- 《Verilog HDL数字系统设计及仿真》第三章源代码-Verilog HDL
Ch4
- 《Verilog HDL数字系统设计及仿真》第四章 Verilog HDL行为级建模源代码-" Verilog HDL design and simulation of digital systems," Chapter IV behavioral modeling Verilog HDL source code
Ch5
- 《Verilog HDL数字系统设计及仿真》第五章任务、函数与编译指令源代码-" Verilog HDL design and simulation of digital systems," Chapter V tasks, functions and compiler directives
Ch6
- 《Verilog HDL数字系统设计及仿真》第六章Verilog HDL测试模块源代码-" Verilog HDL design and simulation of digital systems," Chapter VI test module Verilog HDL source code
Ch7
- 《Verilog HDL数字系统设计及仿真》第七章可综合模型设计源代码-" Verilog HDL design and simulation of digital systems," Chapter VII of the source code can be integrated model design
Ch8
- 《Verilog HDL数字系统设计及仿真》第八章有限状态机的设计源代码-" Verilog HDL design and simulation of digital systems." Chapter VIII of the finite state machine design source code
Ch9
- 《Verilog HDL数字系统设计及仿真》第九章常见功能电路的HDL模型源代码-" Verilog HDL design and simulation of digital systems," Chapter IX common functional circuits HDL model source code
Ch10
- 《Verilog HDL数字系统设计及仿真》第十章完整的设计实例源代码-" Verilog HDL design and simulation of digital systems," Chapter complete design example source code
a_vhd_16550_uart
- 串口模块，带APB接口的。挂载APB总线上可以直接利用。-UART module with APB
sdram
- verilog sdram读写控制，实现数据存储于发送-sdram read and write，data store and communication
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
tel
- 电话用户信令控制器的VHDL实现-Telephone subscriber signaling controller based on VHDL