资源列表
alu
- mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
DE2_LCM_TV
- DE2控制LCD显示电视图像，TRDB-LCM，采用NTSC标准，很有用啊
SDRAMDriver
- sdram接口驱动，按照datasheet基本指令顺序开发，极易理解，但功能上存在一定局限性-sdram interface driver, in accordance with the development of the datasheet basic instruction sequence, easily understood, but there are certain limitations on the functions
uart_niosii
- 在nios环境里面写的uart的程序，调试通过，FPGA选用的是EP2C8Q208C.-Nios environment in which to write the uart of the program, debug through, FPGA chosen is EP2C8Q208C.
chufa
- 四位有符号数字除法 用于basys2板子-divider divider for basys2 sjtu
bypassfull
- half-adder 8-bit using multiplexer
Rom_Control_FPGA
- 用VHDL语言写的ROM控制器，对于编写BUFFER的同志可以用来参考。具有一定价值。-Written in VHDL language using ROM controller, for the preparation of the comrades BUFFER can be used for reference. Has a certain value.
i2c_bus_master
- 自己设计的i2c主功能实现，在周立功逻辑分析仪i2c插件上进行了验证。-I2c of their own design to achieve the main functionality, in the weeks meritorious i2c plug on the logic analyzer has been verified.
Heilbronn_Visit_Design
- 海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述-Heilbronn Visit Design Digital Combination Lock
1
- 基于VHDL的设计实验题目 -VHDL design experiments based on VHDL-based design of experiments subject title
fenpingjiVHDL
- 基于VHDL语言的分频计，QUARTUS II环境-Based on VHDL frequency meter, QUARTUS II environment
OK_pll
- 锁相环，带有测试程序，双进双出，可输入任意参数-Phase-locked loop with a test program, double inlet and outlet, you can enter any parameters