资源列表
FREQU_ER
- 这是一个频率产生的VHDL程序源码，压缩文件，基于EMP7128STC100上运行-This is a frequency of the source VHDL procedures, compressed files, running on EMP7128STC100
microcontroller
- vhdl程序，实现了一个microcontroller,控制数据的数学运算。
TLC7524jiekoudianlu
- 本例为TLC7524接口电路VHDL原程序
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
DE2_Default
- altera DE2自带的默认检测程序 可以测试所有器件-altera DE2 own default testing procedures to test all devices
times
- 计数器，用VHDL实现，先6分频，再10分频，24分频，同时可做万年历-Counter, using VHDL realization frequency first 6 hours, 10 minutes and then the frequency, frequency of 24 minutes, at the same time to do calendar
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过
Verilog
- Verilog三段式状态机描述，本章内容详细的介绍了Verilog三段式状态机描述，进一步加深对Verilog的认识-Verilog descr iption of three-stage state machine, this chapter introduces Verilog detailed descr iption of three-stage state machine, and further deepen the understanding of Verilog 朗读 显
sinout
- VHDL的正弦信号发生器设计，功能大家都知道了！！就不用说了呀-VHDL design of the sinusoidal signal generator, function as we all know it! ! Needless to say it! !
rsencoder
- DVB-C/T调制器的reed-soloman encoder代码-DVB-C/T modulator of reed-soloman encoder code
e4
- 用VHDL实现左右移位寄存器，代码简单，易于实现-left-right shifter
clock2
- this is a sourcecode for a digital clock