资源列表
jtag_uart
- 用verilog 语言写的jtag_uart程序用于实现jtag的串口通信-Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
i2c_core_v02
- I2C FPGA代码，支持master和slave-I2C FPGA code to support master and slave
ps2
- 用VHDL语言实现了PS/2通信协议，PS/2是一种双向同步的串行通信协议。-VHDL language using a PS/2 communication protocol, PS/2 is a two-way synchronous serial communication protocol.
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.
cpu
- This file is desgined for recinfigurable processor
adder
- 自己做的几个不同方式实现的加法器的方法，可以参考一下-Adder several ways to do their own different ways, you can refer to
FAT32
- 基于nios II的FAT32文件系统,SOPC调试通过了的-FAT32 based on nios II
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
pingpang
- 在FPGA的开发中，使用两片外部的SRAM，实现了数据的无缝连接-in the development of FPGA, implement jointless link of data by tow external SRAM.
simplevhdl
- 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3 -8 function decoder and testbench, 16 Register and testbench and traffic li
VHDL
- 自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误
keyscan
- verilog语言 4X4键盘扫描 适合于FPGA、verilog语言的初学者 功能模块分块有条理，清晰。帮助初学者掌握FPGA的分层设计-verilog language； 4X4 keyboard scan for FPGA, verilog language modules for beginners ；block structured and clear. Help beginners master the hierarchical FPGA design