资源列表
parallel_norflash_test
- ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
SEG
- 通过RS232串口进行通信，实现七段数码管记数功能，适合新手入门学习-RS232 serial port for communication, to achieve segment digital tube counting function, suitable for beginners to learn
tiny_tate_bilinear_pairing_latest.tar
- Tiny Tate Bilinear Pairing core is for calculating a special type of Tate bilinear pairing called reduced pairing.-Tiny Tate Bilinear Pairing core is for calculating a special type of Tate bilinear pairing called reduced pairing.
DW8051.tar
- DesignWare 8051 source codes and documentations
stopwatch1
- stopwatch : verilog source code
LM4550_spartanP3a
- 基于XILINX的spartan3a的fpga的嵌入式AC97的IP设计-The spartan3a XILINX fpga based on the design of the IP embedded AC97
FIFO
- 用VERILOG写的FIFO程序，可以直接引用经本人测试-VERILOG written using FIFO procedures, can be directly invoked by the I test
pingball
- Basys开发板上实现的乒乓球游戏代码 很有价值呀！！！运行成功经过测试的-Basys development board table tennis game code to achieve great value it! ! ! After a successful test run
DM9000-debug
- DM9000调试教程，对DM9000的调试有一定帮助。-DM9000 debugging tutorial for DM9000 debug some help.
dianziqin
- 详细列举了电子琴的功能和作用，通过VHDL软件设计的方法方真出其结果，对于提高VHDL有很大的帮助-Keyboards list in detail the functions of the software design, the method by VHDL true out its results, party for improving VHDL has very great help
div_3
- 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)