资源列表
vhdl-primer-bhaskar
- It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students-It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students...
8weicpu
- VHDL语言设计的8位简单的CPU，可以实现包括加法，减法，移位操作，赋值，自加等十多种基本的操作-8 of the VHDL language simple CPU, you can achieve more than 10 kinds of basic operations including addition, subtraction, shift operations, assignment, since Canada
project_wave_gen_code
- 设计并实现一个可产生正弦波、三角波和锯齿波的波形发生器。其工作频率为60MHz，可产生1MHz、2MHz、3MHz、4MHz、5MHz、6MHz、10MHz的正弦波、三角波和锯齿波。所产生波形的幅度、相位均可调整，输出数据的字长为12比特。应用环境为quartus 2-Design and implement a can produce sine, triangle, and sawtooth waveform generator. The operating frequency of 60MH
graph-acceleration-verilog
- 2D图形加速，里面有串口模块。可以综合，为本人毕业设计。-2D graphics acceleration, which has the serial port module. Can be integrated, as my graduation project.
DE2_70_NIOS_14_ssram
- Altera公司DE-70开发板中16位SDRAM的32位用法，纯硬件实现哦-Altera DE-70 16MX16SDRAM =>32bits
Extras_Edge_Detection
- Altera Edge Detection for FPGA
fft_32k
- FFT 32K点设计实例v1.0.0自述文件 本自述文件包含以下部分： 工具要求 o Quartus II编译 o ModelSim仿真模型 o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design exam
mult_16
- 这是自己设计的16位乘法器设计，其中用了booth编码，，4-2压缩器等，-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
digital_tsmc018
- 180nm数字教学库，内含各种标准数字单元-180nm digital lib for education, including standard cells
Extras_Edge_Detection
- ALTERA DE1 SOC VHDL SOURCE CODE
lecture
- 法国工程师学校的VHDL讲义 英文,配有图示和讲解-French engineer school VHDL lecture in English, with icons and explain the
RISC_CPU
- 这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested o