资源列表
UART
- this a uart verilog HDL design code-this is a uart verilog HDL design code
AMS353FD0X_Std_3_5_WVGA_480_800
- Datasheet for samsung AMOLED display AMS353FD0X
vhdl-pipeline-mips_latest.tar
- pipeline mips in vhdl
clock
- 可调式时钟，可对时钟每位进行加减，被调整位闪烁显示-Adjustable clock, each clock can add or subtract, to be adjust-bit flash display
digifilter.tar
- verilog实现的数字滤波器，用于fpga
MCUaFPGA
- 一款MCU及FPGA开发板的整套资料，可供初学者学习-MCU and FPGA development board a set of information for beginners to learn
shudian
- 数电模型的各种代码,基本数电的模型。非常的使用。-digital model
lab14
- DE2平台上实现的数字钟，包含时、分、秒的24小时制时间系统，有校时，准点报时，整点广播等功能。-DE2 platform digital clock, contains, minutes, seconds, 24-hour time system, school, prospective point of time, the whole point of broadcasting.
ddsfinal1
- verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Cymometer
- 用FPGA设计的等精度测量频率。频率的测量范围为1Hz-100MHz。可以测占空比，测时间间隔等。可测正弦波和方波。精度大于10e（-4）-Using FPGA to design the equal precision frequency measurement.Frequency of the measuring range is 1 hz- 100 MHZ.Can examine duty ratio, time interval measurement, etc.Sine wave an
Fre_Counter_verilog
- 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
Altera-datasheet
- altera data sheet for stratix-altera data sheet for stratixII