资源列表
keyscanverilogCX
- 这里有完整的verilog按键消抖程序（经过验证的），有图有真相，本程序是依据特权老师的程序自行改编的，由于按键消抖仿真时间较长，这里是假定16个时钟周期便于仿真。内有详细说明！我在网络上目前只能查找到程序，却找不到仿真程序和解说配套的资料，本文件彻底填补了这一空缺，对于初学者很有帮助！-Here are complete verilog keys away shaking program (proven), picture is truth, this program is based on
elevator_rc1
- 三层电梯控制器，易于扩展，有基本的优先级功能，有灯光提示，VHDL-Three floors elevator controller
uvm_use_pipelined_ahb
- 一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本-one sample example about ahb，include every component and compile scr ipt
VHDL-TFT-LCD
- 使用VHDL语言，控制LCD屏 ,实现显示与屏幕的切换-Using VHDL language, control LCD screen
half
- This is a verilog half adder code
full
- This a full adder verilog code-This is a full adder verilog code
ripple
- This a ripple adder circuit-This is a ripple adder circuit
Carry-Select-Adder
- verilog code for carry select adder
arbitration
- arbiter code in verilog hdl
21_ds1302
- 基于FPGA与DS1302时钟芯片采用Verilog HDL语言编写的数字时钟实现-Based on FPGA and DS1302 clock chip using Verilog HDL language of the digital clock to achieve
dataroad
- VHDL数据通路实验，内容包括：总线通信的基本原则；设备寻址的过程；掌握总线分时复用的方法；掌握多个部件数据通信时数据通路建立过程与控制信号和时序信号的关系。 -VHDL datapath experiments, including: basic principles bus communication Device Addressing process master bus time-multiplexing method grasp the multiple components
text9
- 数字电路实验：计数器。使用小规模集成器件设计计数器的；使用中规模集成器件设计计数器的；Verilog HDL对计数器的建模-Digital circuit experiment: Counter. The use of small-scale integrated device design counter Use medium-scale integrated devices designed to counter Verilog HDL modeling counter