资源列表
nios2irq
- 实现FPGA板上用按钮（外部中断）控制led的亮灭-Implement on FPGA board with button (external interrupt) control the led light out
vga-veriloghdl
- 用Verilog HDL编写的VGA显示驱动程序-大家共同学习-Prepared using Verilog HDL VGA display driver- we learn together
1.-VHDL-Code-For-BCD-To-Decimal-Decoder-By-Data-F
- 1. VHDL Code For BCD To Decimal Decoder By Data Flow Modelling
VHDL-Code-For-Full-Subtractor-By-Data-Flow-Modell
- VHDL Code For Full Subtractor By Data Flow Modelling
VHDL-Code-For-Half-Subtractor-By-Data-Flow-Modell
- VHDL Code For Half Subtractor By Data Flow Modelling
VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling.z
- VHDL Code For Full Adder By Data Flow Modelling
VHDL-Code-For-Half-Adder-By-Data-Flow-Modeling.zi
- VHDL Code For Half Adder By Data Flow Modeling
VHDL-Code-For-BCD-To-Excess3--Code-Converter-By-D
- VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling-VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling
fsk_final
- A simple FSK code using CORDIC sine wave generator.It is basically a switching oscillator kind of Frequency shift keying
VERILOG_FAQ
- Verilog FAQ ------------ This document contains 97 frequently asked questions and their answers related to Verilog. It s for novice to Verilog. But it also useful for intermediate Verilog programmer.
zhong
- 数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。-Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment.
fengming
- VHDL实现蜂鸣器唱歌，已验证通过，音乐文件采用ROM存储。-VHDL implementation buzzer singing, has been verified through.