资源列表
lagrange
- 对原信号进行拉格朗日插值运算，实现信号重采样-The original signal Lagrange interpolation operation, to achieve signal resampling
FPGA2-DSP2-EDMA
- 例程是FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners
AD9288
- AD9288的器件图，参照资料自制。有需要的下载。-AD9288 device diagram, reference information homemade. There is a need to download.
Systemverilog
- 这个为systemverilog 的一个牛人的总结，是初学者必备的，很适合初学者运用的。-This is systemverilog a summary of cattle is essential for beginners, it is suitable for beginners to use.
traffic-light-control-verilog-code
- 交通灯控制器verilog代码，实现交通灯的控制-traffic light control verilog code
self-drink-seller-verilog-code
- 饮料自动售卖机的verilog代码，实现各种情况下饮料的购买-self-drink seller verilog code
serial-port-communication
- 实现串口通信的verilog代码，简述基本串口通信功能的实现-serial port communication verilog code
seria-to-parallel
- 主要用来实现数据串并转换功能，内附2种实现程序-serial to parallel converter verilog code
muti-function-clock
- 用来实现多功能数字钟，可调节闹钟铃声和数码管显示-muti-function digital clock verilog code
telephone-cost-metering
- 该程序用来实现电话计时以算取费用，比较简单-telephone cost metering verilog code
servo
- Verilog编写的辉盛9g舵机控制程序，clk：25MHz，输入角度（0~180），输出PWM，直接连到舵机引脚上即可使用-Verilog prepared Fraser 9g servo control procedures, clk: 25MHz, input angle (0 to 180), the output PWM, directly connected to the steering pin can be used
sata_controller_core_latest.tar
- sata controller core