资源列表
xapp856
- 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
xapp486
- 基于FPGA实现7:1的串行化（含文档）-7:1 Serialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps
3
- 基于FPGA的任意信号发生器，毕业设计完整稿，适合做毕设的同学参考-FPGA-based arbitrary signal generator, a complete draft graduation project, suitable for students to complete reference
vhdl_design
- 介绍VHDL编程技巧，注意事项的好资料。适合接触过vhdl一段时间的人-Introduction VHDL programming skills, good attention to information issues. Vhdl for some time to come into contact with people
clock_counter_vhdl
- 电子时钟VHDL程序与仿真,10进制计数器VHDL程序-clock counter vhdl
URAT_vhdl
- URAT VHDL程序与仿真, UART接收器-uart vhdl sample code
LED_vhdl
- LED控制VHDL程序与仿真,FPGA驱动LED静态显示-led vhdl driver
LCD_vhdl
- LCD控制VHDL程序与仿真, FPGA驱动LCD显示中文字符“年”程序-lcd vhdl driver
shuzizhong
- 1.计时功能采用24小时方式，显示小时、分钟、秒。 2.采用双键校时法，MODE和SET，前者选择始终模式（包括小时、分、秒校时），后者校时脉冲。 3.结果用6个共阳数码管显示。-1. Time functions the way the 24-hour, show hours, minutes, seconds. 2. The use of double bond at the Law School, MODE and SET, always choose the former mod
VerilogHDL
- 华为公司的VHDL语言内训文档，比较简单明了，适合初学者学习。-Huawei House document of the VHDL language, relatively simple and clear, suitable for beginners to learn.
elecfans.com-FPGA_SOPC
- FPGA_SOPC 的例子-Example FPGA_SOPC
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design