资源列表
KIT1234
- This used how to connect the DE2 kit for the external devices-This is used how to connect the DE2 kit for the external devices
Altera
- in file sare karie ,khodeto aziat nakon-in file sare karie ,khodeto aziat nakon......
can_parts
- This the CAN bus controller for implementation inside any FPGA-This is the CAN bus controller for implementation inside any FPGA
1204pointsFFT
- 1024点FFT VHDL实现,含有说明部分，自己好好理解，可自行修改-1024 point FFT VHDL realization that contain part of a good understanding of their own, they are free to modify
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
fir
- 利用Verilog语言编写的FPGA作为数字fir滤波器的程序，在编译器中调试通过，可以作为模块调用。-the model of fir digital cr which is written of verilog language.
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
mult_8b_for
- 本实验使用Verilog语言 通过FOR循环完成8bit乘法器功能，通过ISE仿真测试，可实现综合-Verilog language used in this experiment through the FOR cycle completed 8bit multiplier function, through the ISE simulation tests can be integrated
SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
- VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
seg7led
- 简单的段码的内核测试，已经验证通过，VLOGER编写-A simple paragraph of the core test code has been adopted to verify, VLOGER prepared
multiprocessor
- 简单的乘法器的内核测试，已经验证通过，VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
mem_test
- 简单的存储器内核测试，已经验证通过，VLOGER编写-Simple memory core testing, has been adopted to verify, VLOGER prepared