资源列表
DE2_NET
- 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
DE2_NIOS_HOST_MOUSE_VGA
- 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
DE1_i2sound
- Altera的DE1平台资料，实现de1的音乐播放功能-Altera' s DE1 platform for information, the realization of the music player function de1
bldc_code
- 四轴飞行器的无刷电机驱动的源代码，适用于atmeg8芯片的板子-Four aircraft brushless motor-driven source code, apply to the board atmeg8 chip
DE2_SD_Card_Audio(Modified)
- 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run
dds
- 如何利用FPGA产生DDS调频信号 很具体的-How to make use of DDS generated FM signal FPGA specific
SOPCBuilderIPdesign
- SOPCBuilder用户IP自定义设计，里面讲解了如何按照用户需求自己编写HDL代码来做为v文件，值得参考-SOPCBuilder users to customize the design of IP, which explain how to user needs in accordance with their own HDL code to do the preparation of documents for v, it is also useful
SOPCBuilder
- SOPC Builder教程,其中详细的介绍了SOPC Builder与matlab一起构建系统并加以实现的方案，确实值得一看-SOPC Builder Guide, which describes in detail the SOPC Builder system and build with matlab and the realization of the program is indeed worth a visit
12103321
- 王金明：《VerilogHDL程序设计教程》,pdf电子书,网上辛苦搜集的-Wang Jinming: " VerilogHDL Programming Guide" , pdf e-books, the collection of hard-line ..
FPGAsheijidaquan
- fpga设计常用资料大全，包含常用的FPGA程序资料，对FPGA学习者有很大的帮助。-Encyclopedia of common information fpga design, FPGA that contains commonly used procedures for information on the FPGA is very useful to learners.
Verilog_HDL
- Verilog_HDL_华为入门教程，非常适合于入门学习-Verilog_HDL
DDSyuanma
- DDS波形发生器 (Synplify pro 编译通过)--输出频率 Fout = Fclk*2^M/2^N--分辨率 Fclk/2^N--最大输出频率 Fout = Fclk*50 (理论值,抽样定理)-DDS Waveform Generator (Synplify pro compiler through)- the output frequency Fout = Fclk* 2 ^ M/2 ^ N- Resolution Fclk/2 ^ N- the maximum output fr