资源列表
sp605_IBERT_rdf0036_13.3_c
- 此文件是用所需的时钟缓冲器岁设计示例顶部包装。用户逻辑可以在此包装和岁设计实例化。XILINX官方参考设计。-This file is an example top wrapper for the ibert design with the required clock buffers. User logic can be instantiated in this wrapper along with the ibert design.
0-example_test_board_x
- 本板共有5个LED， 其中D1是板载3.3V指示灯； D2-D5是FPGA的IO口控制；在上电烧录程序后， D1点亮表示电源正常； 其余4个LED依次能够点亮表明硬件完好。-This Board consists of 5 LED, where D1 is the onboard 3.3V indicator D2-D5 FPGA IO mouth control power on after-burning program, D1 point light indicates that pow
12061226project8
- 基于VHDL的多周期cpu模拟，北航作业，已检测可以运行。-cpu simulator
T01_UART_CORE
- Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置，完整工程（xilinx），包括文档、源码等。供学习参考，希望大家上传自己代码，共同提高，*小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation
Ex10_music
- 用CPLD控制音频输出，实现音乐播放的功能，对时序控制。-With CPLD control the audio output to realize the music playback function, timing control.
real_matrix_pkg
- real matrix package is very goood
xilinx_11
- some impurement of Vhdl libary (floating point vs..)
vhdl2008c
- VHDL extension, it is very good for this aim
Verilog-tutorial
- verilog tutorial it is very good tutorial-verilog tutorial it is very good tutorial
verilog
- it is very good tutorial about verilog
Verilog_Tutorial
- it is very good tutorial, it is about vverilog
Lecture6-Bus-Architecture
- simple processor with wirting in vhdl