资源列表
vhdl2005tutorial
- tutorial to VHDL resume
MPSK
- MPSK调制与解调系统设计和VHDL程序与仿真-MPSK modulation and demodulation system design and simulation of VHDL procedures and
MFSK
- MFSK调制系统设计和VHDL程序及仿真-MFSK modulation system design and simulation of VHDL procedures and
MASK
- MASK调制系统设计和VHDL程序及仿真-MASK modulation system design and simulation of VHDL procedures and
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
vhdl_slides
- vhdl课件，缪善林，哈尔滨工程大学信息与通信工程学院-vhdl
SystemC-Tutorial
- systemc 教程,硬件描述语言，交易级建模，语法-systemc tutorial for ground up
cliff_cummings
- cliff cummings的关于VHDL语言的一些经典文章-Useful papers on VHDL language by cliff cummings
dds_9760_OK
- ＤＤＳ信号源程序，用ＶＨＤＬ编的。里面可用拨码开关选择相应的功能：ＦＭ，ＡＳＫ，ＰＳＫ，ＡＭ（这一点实现的不是很好），但其它的很好。频率可达２５Ｍ-DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequen
Muliterfovhdl
- 基于vhdl硬件描述语言的快速乘法器设计-Muilter for vhdl
etester_zcx1002
- 这是一个等精度频率计的VHDL源程序，里面有QuartusII的完整工程文件。-This is a precision frequency meter, such as the VHDL source code, which has a complete project file QuartusII.
cpld
- 基于CPLD的总线控制逻辑，完全正确经调试-CPLD-based control logic of the bus, completely correct by the debug