资源列表
fifo_test.v.tar
- code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
mentor.tar
- high speed counter that is designed to work at 150MHz.
all
- 利用VHDL程式達到上數9999 並且有遮沒+防彈跳功能，是個很好又實際的程式。-Reached on the use of VHDL program and the number of 9999 did not cover+ anti-bounce function is a very good and practical programs.
timeclock
- 基于FPGA实现的简单的时钟，只具有时钟的基本功能。-FPGA-based realization of the simple clock, only the basic functions of the clock.
checksum_master_onchip2.7z
- 学习sopc builder当中自定制元件的最经典最全面的例子，绝对超值-Learning sopc builder customized component among the most classic examples of the most comprehensive, the absolute value
ourdev_185208
- 本讲义主要是讲的Verilog语言，是东南大学讲义，可以对这门语言有个初步的了解。-The lectures are mainly talking about Verilog language, the Southeast University, notes that this language has a basic understanding of.
key
- cyclone系列下，采用计数器现实案件消抖的verilog HDL语言源码-series under the cyclone, the consumer cases Buffeting counter the reality of the verilog HDL language source code! !
sdram_verilog
- sdram的使用，使用verilog HDL来实现对sdram的操作！对时序和语言功底有要求！-sdram use verilog HDL used to achieve operation of the sdram! On the timing and language skills required!
state
- verilog HDL下有限状态机（FSM），麻雀虽小，但五脏俱全！值得一看-under the verilog HDL Finite State Machine (FSM), the sparrow may be small, but is a fully-equipped! Worth a visit! !
instmemory
- Instruction memory in VHDL
Example-2-1
- 编译过正确的fpga开发实例，很是适合也新手入门。fpga开发新手间的交流-fpga
Example-3-1
- 经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。-fpga exampe