资源列表
FIFO_V2
- its a Fifo BASED design i also Interface DAC2904
ram
- 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
VHDL
- VHDL设计实体的基本结构 VHDL的语言要素 用VHDL实现电路设计的方法 VHDL设计流程-VHDL design entities, the basic structure of the language element of VHDL using VHDL circuit design approach to achieve VHDL design flow
sequencedetector
- verilog code for 3 bit sequence detector
rs_enc
- Verilog code for RS-(255,239) encoder.
z
- 描述 Sramoc ( K , M ) 表示用数字0、1、2…、K-1组成的自然数中能被M整除的最小数。给定 K、M，求Sramoc ( K,M )。例如 K=2，M=7的时候，Sramoc( 2 , 7 ) = 1001。 输入 第一行为两个整数K、M满足2<=K<=10、1<=M<=1000。 输出 输出Sramoc(K,M)。 样例输入 2 7 样例输出 1001-Descr
xapp923
- xapp from xilinx very hard to find and very usefull application note from the great firm from USA
newdds
- 基于FPGA的DDS算法的实现，已经通过FPGA的后端仿真实现-FPGA-based algorithm cordic, has passed the back-end FPGA simulation
Decoder
- 这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
adder
- verilog for full_adder
simple_verilog
- cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit