资源列表
19854799dul_ram(yk)
- 双口RAM的FPGA源码Altera 活XIinx或ATmel公司都可以-Dual-port RAM of the FPGA source
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
oc8051.tar
- 8051 core writen in VHDL, fully functional and tested
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost eve
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt gene
usart_verilog
- Uart verilog 代码 可综合 很好的代码-Uart verilog code
stopwatch
- 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
rd_wr_control
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
tx_buff
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
rec_buf
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
HDB3
- hdb3的编解码实现，用c表述的 实际应用性不强，只为说明原理。-HDB3 codec realize, with the practical application of c expression is not strong, only to illustrate the principle.
75448172geleicounter
- 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition