资源列表
32-bit_multiplier_model
- 32-bit_multiplier_model程序，可以直接拿来使用-32-bit_multiplier_model procedures, can be directly used to use
modelsim_ddr2sdram_spartan3s700an.tar
- Modelsim DDR2 SDRAM files
divisor_ITA_VHDL.tar
- Divisor do Tipo com restaura莽茫o sequencial
key
- 键扫描 处理程序 verilog 使用时钟为50Hz // 低电平为按下,高电平为断开 // 输出状态,1为键入,0为无键-Key scanning process using the clock for Verilog 50Hz// low level for the press, high for the disconnect// output state, one for the type, 0 for no key
boothmultiplier
- verilog code for 8-bit signed integers....its working
afg
- this is a docoument of education!
VHDL-8031-IPCore
- this a ipcode of 51 mcu!-this is a ipcode of 51 mcu!
quartus2_manual
- FPGA设计用工具QUARTUS II的使用说明文档-FPGA design tools QUARTUS II the use of documentation
VHDL.Programming.by.Example.4th.Ed
- VHDL.Programming.by.Example第四版，VHDL语言入门书籍-VHDL.Programming.by.Example fourth edition, VHDL language entry-books
ElectronicCodeLock
- 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting
clock
- 用VHDL语言写的实时时钟 用数码管显示 基于的控制芯片是EP1C6Q24C08-VHDL language used to write the real-time clock with digital display are based on the control chip EP1C6Q24C08