资源列表
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
counter
- Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You can stop counting by pressing sequence. I called it detonation clock :]
lift
- VHDL driver of lift in building. Result is presents on LED segments[decimal value].
FPGADFPlabfiles
- 如何使用ISE和FPGA使用指南里面附带许多实验-How to use the ISE and FPGA UserGuide, which fringe much experimental
li123
- 本程序是为出租车设计的，主要功能是出租车自动计费-This procedure is designed for the taxi, taxis are the main functions of automatic billing
RSencode
- 基于FPGA的RS编译码器实现 我是新手 刚学的写的很简单的代码 -FPGA implementation RS codecs
SM2100
- 基于CPLD的增量式光电码盘SOPC使用手册-CPLD-based incremental photoelectric encoder SOPC Manual
binary_to_decima
- 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption，MAX+ plus Ⅱ can be used to run test
61EDA_D954
- 用FPGA实现的ADC采样器,用vhdl编写，spi总线-FPGA implementation using the ADC sampler, prepared using VHDL, spi bus
Programming
- 异步置位复位D触发器，基于VHDL硬件描述语言的仿真。-Set asynchronous reset D flip-flop, based on the VHDL hardware descr iption language simulation.
fpga2
- fpga 基础篇 对初学者有用 好好看看 挺好-fpga
FPGA
- FPGACPLD数字电路设计经验分享，CPLD digitalcircuitdesignexperiencetoshare-FPGACPLDdigitalcircuitdesign experiencetoshare