资源列表
Verilog_HDL
- 华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 -Huawei Documents " basic Verilog Hardware Descr iption Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outl
Fundamentals.of.Digital.Logic.with.VHDL-source.ZIP
- <数字逻辑与VHDL设计>代码 作者：STEPHEN BROWN，ZVONKO VRANESIC 边计年译 -《Fundamentals of Digital Logic with VHDL》 [Brown,Vranesic-2005] code Bian Jinian Translation
Verilog_for_FIFO
- 利用Verilog语言进行FIFO设计，在FPGA中实现32X8FIFO功能-FIFO using Verilog language design, in the FPGA to achieve 32X8FIFO function
x1Altera_uart_VHDL
- 经典UART程序，通用异步收发器设计的vhdl语言,帮助大家学习UART知识-UART classical procedures, UART VHDL design language, to help everyone study UART knowledge
x2uart-all
- 适用异步收发器设计的vhdl语言,是学习UART知识的好例程-Asynchronous Receiver Transmitter apply VHDL design language, are a good knowledge of study UART routines
x3uart
- 学习UART知识，经典UART程序，通用异步收发器设计的vhdl语言-UART study of knowledge, classical UART procedures, UART VHDL design language
68K_ebiu
- It contains a vhdl descr iption of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
master_verilogHDL
- < 精通VerilogHDL IC设计核心技术实例详解>>一书的附录源代码。-< < Proficient in core technology VerilogHDL IC design examples explain> > Appendix 1 of the book source code.
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
daout-Sine-wave
- 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging
ARM7_core
- ARM7内核,vhdl源码形式，不可多的的好东西。-ARM7 core, vhdl source code form, not the many good things.