资源列表
lab6-3-8DECODER
- 数字设计和计算机体系结构：用verilog语言描述3-8译码器的设计与实现-Digital design and computer architecture: use verilog language describe 3-8 decoder design and implementation
udpip
- 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.
snake
- 自己写的verilog贪吃蛇程序，使用vivado2015.2软件编写综合的，硬件平台是xilinx的basys3平台，当检测到碰撞时，led灯会亮起-Write your own verilog Snake program, using the software to prepare a comprehensive vivado2015.2, the hardware platform is the basys3 xilinx platform, when a collision is det
lcd16x2_ctrl
- lcd16*2初始化源码，verilog 可直接引用-lcd16*2 initialization
div84
- An 8-Bit Divider using a Procedure
m2s050-som-fg484-1a
- Microsemi M2SSOM KIT Project
CAN-IP
- CAN控制器IP核(可直接在Nios II中使用)-CAN controller IP core (Nios II can be used directly in the middle)
uart
- VHDL语言模拟异步串口程序，实测可用，欢迎下载-uart source design by FPGA
Extras_Edge_Detection
- ALTERA DE1 SOC VHDL SOURCE CODE
rsencoder.tar
- RS Encoder RTL verilog Code
ultimate_crc.tar
- Ultimate CRC Check RTL Verilog Code
pcpu_handle_mem
- Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU