资源列表
VER_I2C_EEPROM.ZIP
- EEPROM 的verilog仿真模型（cat24cxx系列）-verilog simulition Model of EEPROM,include cat24cxx
eetop.cn_Uvm_spi_bl_reg_tb
- uvm apb verification env
fifo
- FIFO是通过时钟来确定是同步还是异步的，同步FIFO的读写操作是通用一个时钟来控制的。另一方面。两个不同频率或者不同香味的时钟来控制异步FIFO的读写操作。 异步FIFO 跨越时钟域的同步问题-FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other ha
IIR
- IIR滤波器是线性数字滤波器中最常见的一种类型。在一个给定的时间上IIR的输入依赖于它们的输入和先前的输出值。-IIR digital filter is a linear filter is the most common type. At a given time IIR input depending on their previous input and output values.
8b10b_endecode
- 8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-an 8b10b decoder, based on files Martin R and IBM paper
X4_8B10B
- 4倍转换率的8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-8b 4 times the conversion rate of turn 10b encoding and decoding procedures have been verified. ALTERA official code, encoding and decoding two files
crc
- 用于ethernet的CRC校验源代码，ALTERA官方代码，已验证-CRC checksum of the source code for ethernet, ALTERA official code, verified
verilog_uart
- verilog编写的uart源代码，altera官方代码，已验证-verilog prepared uart source code, altera official code, verified
double_addsub
- 双字的加减法的verilog源代码和testbench，已经过测试-verilog source code and testbench double word addition and subtraction, and has been tested
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested