资源列表
38d7dd72-eb79-40e9-b362-77110e0ab3b9
- 基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有-The octave-based EDA player automatically have a flower design language VHDL design
vhdl
- vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing
Verilog_Example
- 设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend
FPGA3.~(6).SchDoc.Zip
- 一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver
i2c_Verilog
- Verilog开发的I2c接口模块，如何需要更详细的资料，请参考www.opencores.org网站-Verilog development I2C interface module, how the need for more detailed information, please refer to website www.opencores.org
password_lock
- 电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
alarm_system
- 电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
an_jian_qu_dou_dong
- 可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
I2C
- I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.
usb_jtag
- FPGA、CPLD芯片的usb数据下载线，下载速度是并口的5位，内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in