资源列表
dispdecoder
- verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
counter
- verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Chapter
- xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company
usb_xilinx_vhdl
- uwb的vhdl语言实现,世间难得啊-UWB realize the VHDL language, rare earth ah
ddc_sim
- Digital downconvertor simulator
FM_Modulation
- FM modulution implement
AM_Modulation
- Am modulation implement fpga
LFSR
- lfsr implement in fpga
VHDLreference
- 英文版的VHDL黄金参考手册，文章中解答了很多关于实际设计中遇到的问题-English version of the VHDL Golden Reference Manual, the article answers a lot about the actual design problems encountered
usb_funct[1].tar
- usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
pud
- Design of 16 bit Filter using VHDL