资源列表
a8254
- 自己编写的8254计数器／计时器，实现了所有的６种模式，和大家一起分享。-I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
VERILOGHDL
- this a book about the verilog-hdl design and circuit simulation and synthesize example
8259
- 8259中断控制器，参考网上的源码，但自己已经调通，并且应用在控制卡和通信卡上。-8259 interrupt controller, online reference source, but he had transferred Qualcomm, and applications in the control card and communication card.
bintoBCD
- 介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera
1_LAB
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
EX
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
DE2Project_restored
- 一个完整的设计DE2_project,希望对大家有所帮助，谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok
hdl
- 这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
CHWCNTACORA
- VHDL编程语言设计，显示灯，显示VHDL字样。-VHDL programming language design, indicator lights, indicating the word VHDL.
dispselect
- verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options
gate_control
- verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control