资源列表
f50k
- VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners
Key
- 具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use o
dianzhenhanzixianshi
- 点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊-Dot-matrix characters shown in the original VHDL program. Comprehensive experimental program procedures, can be used to hope you will support the ah
0-99jishu
- 0-99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦 -0-99 notation VHDL source, comprehensive guide book on the experiment can be used by everyone to download Oh
shiftdata
- 双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you
REG8
- 寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn
ram_r_w
- 用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language descr iption of the memory read and write, user-friendly, simple and practical.
dram_controller
- 用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL descr iption Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
FPGA_and_CPLD_VHDL_GB
- VHDL数字电路设计的电子书，很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
cf_fft_1024_8
- 这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t
verilog
- Verilog 经典实例，完整源码与大家分享-Verilog classic example of a complete source to share with you
89c51
- 利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source