资源列表
shc
- 自己想的写的。。是毕业时候用到。的、、谢谢大家-They want to write. . When used graduation. , And, thank you to see
vgatutorial13
- 这个主要是用VHDL语言来实现从xilinxFPGA中的RBOM中读取一幅图像，并通过VGA口显示出来，同时还有加密的功能，按不同的按键可以实现图像颜色转换。-The VHDL language is mainly used in the RBOM from a xilinxFPGA to read an image, and displayed through the VGA port, as well as the function of encryption, the keys can b
verilog_74_2
- 74HC161，74HC194，74HC283，74hc4017，Verilog实现，带实验说明文档。-74HC161, 74HC194, 74HC283, 74hc4017, Verilog implementation, with test documentation.
99-down-count
- 99倒数计数器，利用EDA的专用软体quartus II来编写，程序功能为99倒数计数器，可以自动清0.-99 down counter
Modelsim
- Modelsim 5.6詳細使用教學手冊-Of Modelsim 5.6 using the instruction manual
PID
- PID控制，采用VHDL代码实现，整个实体模块由三个vhdl文件组成，仅供参考和学习；-PID control, the use of VHDL code, the entire entity vhdl module consists of three files, for reference and learning
modelsim57e
- Verilog编写仿真软件，能很好的仿真其他环境的已编译文件-modelsim
ethtoe1
- 硕士论文 基于FPGA的Ethernet+over+E1接口芯片的设计与实现.pdf-master paper the design and implentation of Ethernet+over+E1
DAC8812
- DA转换，Verilog HDL 编的，可实现DA转化。DA芯片用的是DAC8812，实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
ultrasonic
- 此源程序代码为基于ＶＨＤＬ语言的超声波检测的软件代码-This source code for VHDL-based ultrasonic testing of software code
CPLD-CRACK-SIEMENS-200PLC
- 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the
Electronic-Clock_1.11
- 用quartusii 设计的电子钟原型文件-Electronic clock with quartusii prototype file design