资源列表
Encoder_8X3
- verilog code of 8X3 Encoder.
MUX_8X1
- Verilog code for 8X1 Multiplexer
PWM
- 此程序利用FPGA芯片的内部时钟，根据输入信号，产生占空比可调的方波信号。-This program uses the FPGA chip s internal clock, according to the input signal to generate variable duty cycle square wave signal.
UART_FPGA
- 此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。-This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the ba
LSP
- THIS CODE IS FOR COMPUTING LSP USING HARDWARE REALIZATION IN TERMS OF MUX AND FF.
LSP-NEW
- THIS FOR UPDATING CODE FOR LSP.-THIS IS FOR UPDATING CODE FOR LSP.
BARREL-NEW
- THIS USED TO STORE VALUES i.e barrel-THIS IS USED TO STORE VALUES i.e barrel
PISO-NEW
- THIS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.-THIS IS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.
binary
- this is for low power dsp for wireless nodes (binary tree computation)
scaling
- A camera raw image file contains minimally processed data the image sensor of either a digital camera, image scanner, or motion picture film scanner. Raw files are named so because they are not yet processed and therefore are not ready to be printed
3Digit_7segment_ind_decoder
- 3 Digit BCD to 7 segment indicator decoder
ADC_AD7366_poll
- Module for AD7366 ADC po-Module for AD7366 ADC poll